The gm/ID Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits (Registro nro. 198070)

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International Standard Book Number 9780387471013
-- 978-0-387-47101-3
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Classification number TK7888.4
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Classification number 621.3815
Edition number 23
100 1# - ASIENTO PRINCIPAL--NOMBRE PERSONAL
Personal name Jespers, Paul.
Relator term author.
245 14 - MENCIÓN DE TITULO
Title The gm/ID Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits
Medium [recurso electrónico] :
Remainder of title The semi-empirical and compact model approaches /
Statement of responsibility, etc. by Paul Jespers.
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture Boston, MA :
Name of producer, publisher, distributor, manufacturer Springer US,
Date of production, publication, distribution, manufacture, or copyright notice 2010.
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Extent XVI, 171p.
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Media type term computer
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490 1# - MENCIÓN DE SERIE
Series statement Analog Circuits and Signal Processing
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Summary, etc. How to determine transistor sizes and currents when the supply voltages of analog CMOS circuits do not exceed 1.2V and transistors operate in weak, moderate or strong inversion? The gm/ID methodology offers a solution provided a reference transconductance over drain current ratio is available. The reference may be the result of measurements carried out on real physical transistors or advanced models. The reference may also take advantage of a compact model. In The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits, we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests.
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Topical term or geographic name as entry element Engineering.
650 #0 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO
Topical term or geographic name as entry element Computer science.
650 #0 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO
Topical term or geographic name as entry element Systems engineering.
650 14 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO
Topical term or geographic name as entry element Engineering.
650 24 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO
Topical term or geographic name as entry element Circuits and Systems.
650 24 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO
Topical term or geographic name as entry element Processor Architectures.
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Topical term or geographic name as entry element Solid State Physics.
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Topical term or geographic name as entry element Spectroscopy and Microscopy.
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Title Springer eBooks
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Relationship information Printed edition:
International Standard Book Number 9780387471006
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Uniform title Analog Circuits and Signal Processing
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Public note Libro electrónico
Uniform Resource Identifier <a href="http://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-0-387-47101-3">http://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-0-387-47101-3</a>
942 ## - TIPO DE MATERIAL (KOHA)
Koha item type Libro Electrónico
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