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04908nam a22004695i 4500 |
| 001 - NÚMERO DE CONTROL |
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| 003 - IDENTIFICADOR DEL NÚMERO DE CONTROL |
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| 005 - FECHA Y HORA DE LA ULTIMA TRANSACCIÓN |
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20160812080116.0 |
| 007 - CAMPO FIJO DE DESCRIPCIÓN FIJA--INFORMACIÓN GENERAL |
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| 008 - ELEMENTOS DE LONGITUD FIJA -- INFORMACIÓN GENERAL |
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100301s2010 xxu| s |||| 0|eng d |
| 020 ## - NÚMERO INTERNACIONAL NORMALIZADO PARA LIBROS |
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| International Standard Book Number |
9781441909503 |
| -- |
978-1-4419-0950-3 |
| 040 ## - FUENTE DE CATALOGACIÓN |
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| Transcribing agency |
MX-MeUAM |
| 050 #4 - SIGNATURA TOPOGRÁFICA DE LA BIBLIOTECA DEL CONGRESO |
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| Classification number |
TK7888.4 |
| 082 04 - NÚMERO DE CLASIFICACIÓN DECIMAL DEWEY |
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| Classification number |
621.3815 |
| Edition number |
23 |
| 100 1# - ASIENTO PRINCIPAL--NOMBRE PERSONAL |
|---|
| Personal name |
Jayakumar, Nikhil. |
| Relator term |
author. |
| 245 10 - MENCIÓN DE TITULO |
|---|
| Title |
Minimizing and Exploiting Leakage in VLSI Design |
| Medium |
[recurso electrónico] / |
| Statement of responsibility, etc. |
by Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
|---|
| Place of production, publication, distribution, manufacture |
Boston, MA : |
| Name of producer, publisher, distributor, manufacturer |
Springer US, |
| Date of production, publication, distribution, manufacture, or copyright notice |
2010. |
| 300 ## - DESCRIPCIÓN FÍSICA |
|---|
| Other physical details |
online resource. |
| 336 ## - CONTENT TYPE |
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| Content type term |
text |
| Content type code |
txt |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
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| Media type term |
computer |
| Media type code |
c |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
|---|
| Carrier type term |
online resource |
| Carrier type code |
cr |
| Source |
rdacarrier |
| 347 ## - DIGITAL FILE CHARACTERISTICS |
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| File type |
text file |
| Encoding format |
PDF |
| Source |
rda |
| 505 0# - NOTA DE CONTENIDO |
|---|
| Formatted contents note |
Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes -- Existing Leakage Minimization Approaches -- Computing Leakage Current Distributions -- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities -- The HL Approach: A Low-Leakage ASIC Design Methodology -- Simultaneous Input Vector Control and Circuit Modification -- Optimum Reverse Body Biasing for Leakage Minimization -- I: Conclusions and Future Directions -- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design -- Exploiting Leakage: Sub-threshold Circuit Design -- Adaptive Body Biasing to Compensate for PVT Variations -- Optimum VDD for Minimum Energy -- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining -- II: Conclusions and Future Directions -- Design of a Sub-threshold BFSK Transmitter IC -- Design of the Chip -- Implementation of the Chip -- Experimental Results. |
| 520 ## - NOTA DE RESUMEN, ETC. |
|---|
| Summary, etc. |
Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book. Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage. Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes). |
| 596 ## - |
|---|
| -- |
19 |
| 650 #0 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Engineering. |
| 650 #0 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Computer aided design. |
| 650 #0 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Systems engineering. |
| 650 14 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Engineering. |
| 650 24 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Circuits and Systems. |
| 650 24 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Computer-Aided Engineering (CAD, CAE) and Design. |
| 700 1# - ASIENTO SECUNDARIO - NOMBRE PERSONAL |
|---|
| Personal name |
Paul, Suganth. |
| Relator term |
author. |
| 700 1# - ASIENTO SECUNDARIO - NOMBRE PERSONAL |
|---|
| Personal name |
Garg, Rajesh. |
| Relator term |
author. |
| 700 1# - ASIENTO SECUNDARIO - NOMBRE PERSONAL |
|---|
| Personal name |
Gulati, Kanupriya. |
| Relator term |
author. |
| 700 1# - ASIENTO SECUNDARIO - NOMBRE PERSONAL |
|---|
| Personal name |
Khatri, Sunil P. |
| Relator term |
author. |
| 710 2# - ASIENTO SECUNDARIO - NOMBRE CORPORATIVO |
|---|
| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
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| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Printed edition: |
| International Standard Book Number |
9781441909497 |
| 856 40 - LOCALIZACIÓN Y ACCESO ELECTRÓNICOS |
|---|
| Public note |
Libro electrónico |
| Uniform Resource Identifier |
<a href="http://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-1-4419-0950-3">http://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-1-4419-0950-3</a> |
| 942 ## - TIPO DE MATERIAL (KOHA) |
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| Koha item type |
Libro Electrónico |
