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001 - NÚMERO DE CONTROL |
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20160812084047.0 |
007 - CAMPO FIJO DE DESCRIPCIÓN FIJA--INFORMACIÓN GENERAL |
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110517s2011 xxu| s |||| 0|eng d |
020 ## - NÚMERO INTERNACIONAL NORMALIZADO PARA LIBROS |
International Standard Book Number |
9781441993595 |
-- |
978-1-4419-9359-5 |
040 ## - FUENTE DE CATALOGACIÓN |
Transcribing agency |
MX-MeUAM |
050 #4 - SIGNATURA TOPOGRÁFICA DE LA BIBLIOTECA DEL CONGRESO |
Classification number |
TK7888.4 |
082 04 - NÚMERO DE CLASIFICACIÓN DECIMAL DEWEY |
Classification number |
621.3815 |
Edition number |
23 |
100 1# - ASIENTO PRINCIPAL--NOMBRE PERSONAL |
Personal name |
Kundu, Sudipta. |
Relator term |
author. |
245 10 - MENCIÓN DE TITULO |
Title |
High-Level Verification |
Medium |
[recurso electrónico] : |
Remainder of title |
Methods and Tools for Verification of System-Level Designs / |
Statement of responsibility, etc. |
by Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta. |
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
Place of production, publication, distribution, manufacture |
New York, NY : |
Name of producer, publisher, distributor, manufacturer |
Springer New York, |
Date of production, publication, distribution, manufacture, or copyright notice |
2011. |
300 ## - DESCRIPCIÓN FÍSICA |
Extent |
XIII, 167 p. |
Other physical details |
online resource. |
336 ## - CONTENT TYPE |
Content type term |
text |
Content type code |
txt |
Source |
rdacontent |
337 ## - MEDIA TYPE |
Media type term |
computer |
Media type code |
c |
Source |
rdamedia |
338 ## - CARRIER TYPE |
Carrier type term |
online resource |
Carrier type code |
cr |
Source |
rdacarrier |
347 ## - DIGITAL FILE CHARACTERISTICS |
File type |
text file |
Encoding format |
PDF |
Source |
rda |
505 0# - NOTA DE CONTENIDO |
Formatted contents note |
Introduction -- Related Work -- Background -- Execution-based Model Checking for High-Level Designs -- Efficient Symbolic Analysis for Concurrent Programs -- Translation Validation of High-Level Synthesis -- Parameterized Program Equivalence Checking -- Conclusions and Future Work. |
520 ## - NOTA DE RESUMEN, ETC. |
Summary, etc. |
This book looks at the problem of design verification with a view towards speeding up the process of verification by developing methods that apply to levels of abstraction above RTL or synchronous logic descriptions. Typically such descriptions capture design functionality at the system level, hence the topic area is also referred to as system level verification. Since such descriptions can also capture software, especially device drivers or other embedded software, this book will be of interest to both hardware and software designers. ? The methodology presented in this book relies upon advances in synthesis techniques, as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL. Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification; Uses a combination of formal techniques to do scalable verification of system designs completely automatically; Presents techniques that guarantee properties verified in the high-level design are preserved through the translation to low-level RTL; Written by researchers working in mainstream hardware and software design and includes results from both academia and industry ? ? ? |
596 ## - |
-- |
19 |
650 #0 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
Topical term or geographic name as entry element |
Engineering. |
650 #0 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
Topical term or geographic name as entry element |
Computer aided design. |
650 #0 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
Topical term or geographic name as entry element |
Systems engineering. |
650 14 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
Topical term or geographic name as entry element |
Engineering. |
650 24 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
Topical term or geographic name as entry element |
Circuits and Systems. |
650 24 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
Topical term or geographic name as entry element |
Computer-Aided Engineering (CAD, CAE) and Design. |
700 1# - ASIENTO SECUNDARIO - NOMBRE PERSONAL |
Personal name |
Lerner, Sorin. |
Relator term |
author. |
700 1# - ASIENTO SECUNDARIO - NOMBRE PERSONAL |
Personal name |
Gupta, Rajesh K. |
Relator term |
author. |
710 2# - ASIENTO SECUNDARIO - NOMBRE CORPORATIVO |
Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
773 0# - HOST ITEM ENTRY |
Title |
Springer eBooks |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Relationship information |
Printed edition: |
International Standard Book Number |
9781441993588 |
856 40 - LOCALIZACIÓN Y ACCESO ELECTRÓNICOS |
Public note |
Libro electrónico |
Uniform Resource Identifier |
<a href="http://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-1-4419-9359-5">http://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-1-4419-9359-5</a> |
942 ## - TIPO DE MATERIAL (KOHA) |
Koha item type |
Libro Electrónico |