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| 001 - NÚMERO DE CONTROL |
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SIRSI |
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20160812084431.0 |
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111114s2011 gw | s |||| 0|eng d |
| 020 ## - NÚMERO INTERNACIONAL NORMALIZADO PARA LIBROS |
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| International Standard Book Number |
9783642245688 |
| -- |
978-3-642-24568-8 |
| 040 ## - FUENTE DE CATALOGACIÓN |
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| Transcribing agency |
MX-MeUAM |
| 050 #4 - SIGNATURA TOPOGRÁFICA DE LA BIBLIOTECA DEL CONGRESO |
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| Classification number |
QA76.9.C62 |
| 082 04 - NÚMERO DE CLASIFICACIÓN DECIMAL DEWEY |
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| Classification number |
004 |
| Edition number |
23 |
| 100 1# - ASIENTO PRINCIPAL--NOMBRE PERSONAL |
|---|
| Personal name |
Stenström, Per. |
| Relator term |
editor. |
| 245 10 - MENCIÓN DE TITULO |
|---|
| Title |
Transactions on High-Performance Embedded Architectures and Compilers IV |
| Medium |
[recurso electrónico] / |
| Statement of responsibility, etc. |
edited by Per Stenström. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
|---|
| Place of production, publication, distribution, manufacture |
Berlin, Heidelberg : |
| Name of producer, publisher, distributor, manufacturer |
Springer Berlin Heidelberg, |
| Date of production, publication, distribution, manufacture, or copyright notice |
2011. |
| 300 ## - DESCRIPCIÓN FÍSICA |
|---|
| Extent |
XV, 430p. 222 illus. |
| Other physical details |
online resource. |
| 336 ## - CONTENT TYPE |
|---|
| Content type term |
text |
| Content type code |
txt |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
|---|
| Media type term |
computer |
| Media type code |
c |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
|---|
| Carrier type term |
online resource |
| Carrier type code |
cr |
| Source |
rdacarrier |
| 347 ## - DIGITAL FILE CHARACTERISTICS |
|---|
| File type |
text file |
| Encoding format |
PDF |
| Source |
rda |
| 490 1# - MENCIÓN DE SERIE |
|---|
| Series statement |
Lecture Notes in Computer Science, |
| International Standard Serial Number |
0302-9743 ; |
| Volume/sequential designation |
6760 |
| 505 0# - NOTA DE CONTENIDO |
|---|
| Formatted contents note |
A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors -- Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces -- Compiler Directed Issue Queue Energy Reduction -- A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors -- Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors -- Special Section on High-Performance and Embedded Architectures and Compilers (HiPEAC) -- A Highly Scalable Parallel Implementation of H.264 -- Communication Based Proactive Link Power Management -- Finding Extreme Behaviors in Microprocessor Workloads -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Special Section on Selected papers from the Workshop on Software and Hardware Challenges of Many-core Platforms -- Transaction Reordering to Reduce Aborts in Software Transactional Memory -- A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture -- A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM -- Software Transactional Memory Validation – Time and Space Considerations Tiled Multi-Core Stream Architecture -- An Efficient and Flexible Task Management for Many Cores -- Special Section on International Symposium on Systems, ArchitecturesModeling and Simulation -- On Two-layer Brain-inspired Hierarchical Topologies: A Rent’s Rule Approach -- Advanced Packet Segmentation and Buffering Algorithms in Network Processors -- Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation -- A Cost Model for Partial Dynamic Reconfiguration -- Heterogeneous Design in Functional DIF -- Signature-based Calibration of Analytical Performance Models for System-level Design Space Exploration. |
| 520 ## - NOTA DE RESUMEN, ETC. |
|---|
| Summary, etc. |
Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This 4th issue contains 21 papers carefully reviewed and selected out of numerous submissions and is divided in four sections. The first section contains five regular papers. The second section consists of the top four papers from the 4th International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The third section contains a set of six papers providing a snap-shot from the Workshop on Software and Hardware Challenges of Manycore Platforms, SHCMP 2008 held in Beijing, China, in June 2008. The fourth section consists of six papers from the 8th IEEE International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS VIII (2008) held in Samos, Greece, in July 2008. |
| 596 ## - |
|---|
| -- |
19 |
| 650 #0 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Computer science. |
| 650 #0 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Data transmission systems. |
| 650 #0 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Logic design. |
| 650 #0 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Computer Communication Networks. |
| 650 14 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Computer Science. |
| 650 24 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Arithmetic and Logic Structures. |
| 650 24 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Processor Architectures. |
| 650 24 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Input/Output and Data Communications. |
| 650 24 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Logic Design. |
| 650 24 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Computer Communication Networks. |
| 650 24 - ASIENTO SECUNDARIO DE MATERIA - TERMINO TEMÁTICO |
|---|
| Topical term or geographic name as entry element |
Programming Languages, Compilers, Interpreters. |
| 710 2# - ASIENTO SECUNDARIO - NOMBRE CORPORATIVO |
|---|
| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
|---|
| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Printed edition: |
| International Standard Book Number |
9783642245671 |
| 830 #0 - ASIENTO SECUNDARIO DE SERIE--TITULO UNIFORME |
|---|
| Uniform title |
Lecture Notes in Computer Science, |
| International Standard Serial Number |
0302-9743 ; |
| Volume number/sequential designation |
6760 |
| 856 40 - LOCALIZACIÓN Y ACCESO ELECTRÓNICOS |
|---|
| Public note |
Libro electrónico |
| Uniform Resource Identifier |
<a href="http://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-3-642-24568-8">http://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-3-642-24568-8</a> |
| 942 ## - TIPO DE MATERIAL (KOHA) |
|---|
| Koha item type |
Libro Electrónico |
