MARC details
| 000 -LIDER |
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| fixed length control field |
03095nam a22004815i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
978-81-322-2791-5 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20180206183003.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
160517s2016 ii | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9788132227915 |
| -- |
978-81-322-2791-5 |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
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| Classification number |
TK7888.4 |
| 072 #7 - SUBJECT CATEGORY CODE |
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| Subject category code |
TJFC |
| Source |
bicssc |
| 072 #7 - SUBJECT CATEGORY CODE |
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| Subject category code |
TEC008010 |
| Source |
bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.3815 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Taraate, Vaibbhav. |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
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| Title |
Digital Logic Design Using Verilog |
| Medium |
[recurso electrónico] : |
| Remainder of title |
Coding and RTL Synthesis / |
| Statement of responsibility, etc. |
by Vaibbhav Taraate. |
| 264 #1 - |
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| -- |
New Delhi : |
| -- |
Springer India : |
| -- |
Imprint: Springer, |
| -- |
2016. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
XXIII, 416 p. 267 illus., 226 illus. in color. |
| Other physical details |
online resource. |
| 336 ## - |
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| -- |
text |
| -- |
txt |
| -- |
rdacontent |
| 337 ## - |
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| -- |
computer |
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c |
| -- |
rdamedia |
| 338 ## - |
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| -- |
online resource |
| -- |
cr |
| -- |
rdacarrier |
| 347 ## - |
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| -- |
text file |
| -- |
PDF |
| -- |
rda |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Término temático o nombre geográfico como elemento de entrada |
Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Término temático o nombre geográfico como elemento de entrada |
Logic design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Término temático o nombre geográfico como elemento de entrada |
Electronics. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Término temático o nombre geográfico como elemento de entrada |
Microelectronics. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Término temático o nombre geográfico como elemento de entrada |
Electronic circuits. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Término temático o nombre geográfico como elemento de entrada |
Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Término temático o nombre geográfico como elemento de entrada |
Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Término temático o nombre geográfico como elemento de entrada |
Electronics and Microelectronics, Instrumentation. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Término temático o nombre geográfico como elemento de entrada |
Logic Design. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
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| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
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| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
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| Relationship information |
Printed edition: |
| International Standard Book Number |
9788132227892 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
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| Public note |
Libro electrónico |
| Uniform Resource Identifier |
http://148.231.10.114:2048/login?url=http://dx.doi.org/10.1007/978-81-322-2791-5 |
| 912 ## - |
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| -- |
ZDB-2-ENG |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Koha item type |
Libro Electrónico |
