MARC details
000 -LIDER |
fixed length control field |
03738nam a22005655i 4500 |
001 - CONTROL NUMBER |
control field |
978-3-031-37989-5 |
003 - CONTROL NUMBER IDENTIFIER |
control field |
DE-He213 |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20250516155922.0 |
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
fixed length control field |
cr nn 008mamaa |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
230922s2024 sz | s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9783031379895 |
-- |
978-3-031-37989-5 |
050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
Classification number |
TK7867-7867.5 |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
TJFC |
Source |
bicssc |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
TEC008010 |
Source |
bisacsh |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
TJFC |
Source |
thema |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.3815 |
Edition number |
23 |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Zamiri Azar, Kimia. |
Relator term |
author. |
Relator code |
aut |
-- |
http://id.loc.gov/vocabulary/relators/aut |
245 10 - TITLE STATEMENT |
Title |
Understanding Logic Locking |
Medium |
[electronic resource] / |
Statement of responsibility, etc. |
by Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor. |
250 ## - EDITION STATEMENT |
Edition statement |
1st ed. 2024. |
264 #1 - |
-- |
Cham : |
-- |
Springer International Publishing : |
-- |
Imprint: Springer, |
-- |
2024. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
XVI, 381 p. 1 illus. |
Other physical details |
online resource. |
336 ## - |
-- |
text |
-- |
txt |
-- |
rdacontent |
337 ## - |
-- |
computer |
-- |
c |
-- |
rdamedia |
338 ## - |
-- |
online resource |
-- |
cr |
-- |
rdacarrier |
347 ## - |
-- |
text file |
-- |
PDF |
-- |
rda |
505 0# - FORMATTED CONTENTS NOTE |
Formatted contents note |
Basics of VLSI Design -- Basics of VLSI Testing and Debug -- IP Protection in VLSI Design: A Historical View -- Making a Case for Logic Locking -- Fundamentals of Logic Locking -- Infrastructure around Logic Locking -- Impact of Satisfiability Solvers on Logic Locking -- Post-Satisfiability Era: Countermeasures and Threats -- Design-for-Testability and its Impact on Logic Locking -- Emergence of Cutting-edge Technologies on Logic Locking -- Logic Locking in Future IC Supply Chain Environments -- Multilayer Approach to Logic Locking -- A Step-by-Step Guide for Protecting/Locking Your IP -- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP. |
520 ## - SUMMARY, ETC. |
Summary, etc. |
This book demonstrates the breadth and depth of IP protection through logic locking, considering both attacker/adversary and defender/designer perspectives. The authors draw a semi-chronological picture of the evolution of logic locking during the last decade, gathering and describing all the DO's and DON'Ts in this approach. They describe simple-to-follow scenarios and guide readers to navigate/identify threat models and design/evaluation flow for further studies. Readers will gain a comprehensive understanding of all fundamentals of logic locking. Covers modern VLSI design, testability and debug, and hardware security threats at different levels of abstraction; Provides a comprehensive overview of logic locking techniques and their applications to hardware security; Covers logic locking from implementation to evaluation, different assumptions, models and abstraction layers. |
541 ## - IMMEDIATE SOURCE OF ACQUISITION NOTE |
Owner |
UABC ; |
Method of acquisition |
Perpetuidad |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Término temático o nombre geográfico como elemento de entrada |
Electronic circuit design. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Término temático o nombre geográfico como elemento de entrada |
Embedded computer systems. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Término temático o nombre geográfico como elemento de entrada |
Electronic circuits. |
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Término temático o nombre geográfico como elemento de entrada |
Electronics Design and Verification. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Término temático o nombre geográfico como elemento de entrada |
Embedded Systems. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Término temático o nombre geográfico como elemento de entrada |
Electronic Circuits and Systems. |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Mardani Kamali, Hadi. |
Relator term |
author. |
Relator code |
aut |
-- |
http://id.loc.gov/vocabulary/relators/aut |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Farahmandi, Farimah. |
Relator term |
author. |
Relator code |
aut |
-- |
http://id.loc.gov/vocabulary/relators/aut |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Tehranipoor, Mark. |
Relator term |
author. |
Relator code |
aut |
-- |
http://id.loc.gov/vocabulary/relators/aut |
710 2# - ADDED ENTRY--CORPORATE NAME |
Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
773 0# - HOST ITEM ENTRY |
Title |
Springer Nature eBook |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Relationship information |
Printed edition: |
International Standard Book Number |
9783031379888 |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Relationship information |
Printed edition: |
International Standard Book Number |
9783031379901 |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Relationship information |
Printed edition: |
International Standard Book Number |
9783031379918 |
856 40 - ELECTRONIC LOCATION AND ACCESS |
Public note |
Libro electrónico |
Uniform Resource Identifier |
http://libcon.rec.uabc.mx:2048/login?url=https://doi.org/10.1007/978-3-031-37989-5 |
912 ## - |
-- |
ZDB-2-ENG |
912 ## - |
-- |
ZDB-2-SXE |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Koha item type |
Libro Electrónico |