On-Chip Interconnect with aelite [recurso electrónico] : Composable and Predictable Systems / by Andreas Hansson, Kees Goossens.
Tipo de material:
TextoSeries Embedded SystemsEditor: New York, NY : Springer New York : Imprint: Springer, 2011Descripción: X, 210 p. online resourceTipo de contenido: text Tipo de medio: computer Tipo de portador: online resourceISBN: 9781441968654Tema(s): Engineering | Computer aided design | Systems engineering | Engineering | Circuits and Systems | Computer-Aided Engineering (CAD, CAE) and DesignFormatos físicos adicionales: Printed edition:: Sin títuloClasificación CDD: 621.3815 Clasificación LoC:TK7888.4Recursos en línea: Libro electrónico
En: Springer eBooksResumen: On-Chip Interconnect with aelite: Composable and Predictable Systems by: (Authors) Andreas Hansson Kees Goossens Embedded systems are comprised of components integrated on a single circuit, a System on Chip (SoC). One of the critical elements of such an SoC, and the focus of this work, is the on-chip interconnect that enables different components to communicate with each other. The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs. •Uses real-world illustrations extensively, in the form of case studies and examples that communicate the power of the methods presented; •Uses one consistent, running example throughout the book. This example is introduced in the introductory chapter and supports the presentation throughout the work, with additional details given in each chapter; •Content has both breadth (architecture, resource allocation, hardware/software instantiation, formal verification) and depth (block-level architecture description, allocation algorithms, complete run-time APIs, detailed formal models, complete case studies mapped to FPGAs); •Includes numerous case studies, e.g. a JPEG decoder, set-top box and digital radio design.
| Tipo de ítem | Biblioteca actual | Colección | Signatura | Copia número | Estado | Fecha de vencimiento | Código de barras |
|---|---|---|---|---|---|---|---|
| Libro Electrónico | Biblioteca Electrónica | Colección de Libros Electrónicos | TK7888.4 (Browse shelf(Abre debajo)) | 1 | No para préstamo | 371764-2001 |
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| TK7888.4 Dependability in Electronic Systems | TK7888.4 Ultra Low-Power Integrated Circuit Design for Wireless Neural Interfaces | TK7888.4 Design and Analysis of Biomolecular Circuits | TK7888.4 On-Chip Interconnect with aelite | TK7888.4 Low Power Networks-on-Chip | TK7888.4 Analog Layout Synthesis | TK7888.4 Software Automatic Tuning |
On-Chip Interconnect with aelite: Composable and Predictable Systems by: (Authors) Andreas Hansson Kees Goossens Embedded systems are comprised of components integrated on a single circuit, a System on Chip (SoC). One of the critical elements of such an SoC, and the focus of this work, is the on-chip interconnect that enables different components to communicate with each other. The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs. •Uses real-world illustrations extensively, in the form of case studies and examples that communicate the power of the methods presented; •Uses one consistent, running example throughout the book. This example is introduced in the introductory chapter and supports the presentation throughout the work, with additional details given in each chapter; •Content has both breadth (architecture, resource allocation, hardware/software instantiation, formal verification) and depth (block-level architecture description, allocation algorithms, complete run-time APIs, detailed formal models, complete case studies mapped to FPGAs); •Includes numerous case studies, e.g. a JPEG decoder, set-top box and digital radio design.
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