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Quality-Driven SystemC Design [recurso electrónico] / by Daniel Große, Rolf Drechsler.

Por: Große, Daniel [author.]Colaborador(es): Drechsler, Rolf [author.] | SpringerLink (Online service)Tipo de material: Texto

TextoEditor: Dordrecht : Springer Netherlands, 2010Descripción: XIX, 170 p. online resourceTipo de contenido: text Tipo de medio: computer Tipo de portador: online resourceISBN: 9789048136315Tema(s): Engineering | Computer science | Software engineering | Systems engineering | Engineering | Circuits and Systems | Software Engineering/Programming and Operating Systems | Register-Transfer-Level ImplementationFormatos físicos adicionales: Printed edition:: Sin títuloClasificación CDD: 621.3815 Clasificación LoC:TK7888.4Recursos en línea: Libro electrónico Texto

Contenidos:

Preliminaries -- System-Level Verification -- Block-Level Verification -- Top-Level Verification -- Summary and Conclusions.

En: Springer eBooksResumen: Faced with the steadily increasing complexity and rapidly shortening time-to-market requirements designing electronic systems is a very challenging task. To manage this situation effectively the level of abstraction in modeling has been raised during the past years in the computer aided design community. Meanwhile, for the so-called system-level design the system description language SystemC has become the de facto standard. However, while modeling from abstract to synthesizable descriptions in combination with specification concepts like Transaction Level Modeling (TLM) leads to very good results, the verification quality is poor. The two main reasons are that (1) the existing SystemC verification techniques do not escort the different abstraction levels effectively and (2) in particular the resulting quality in terms of the covered functionality is only checked manually. Hence, due to the increasing design complexity the number of undetected errors is growing rapidly. Therefore a quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.

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Notas de título ( 3 )

Existencias
Tipo de ítem	Biblioteca actual	Colección	Signatura	Copia número	Estado	Fecha de vencimiento	Código de barras
Libro Electrónico	Biblioteca Electrónica	Colección de Libros Electrónicos	TK7888.4 (Browse shelf(Abre debajo))	1	No para préstamo		377666-2001

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Previo	TK7888.4 Models in Hardware Testing	TK7888.4 Efficient Test Methodologies for High-Speed Serial Links	TK7888.4 Dynamically Reconfigurable Systems	TK7888.4 Quality-Driven SystemC Design	TK7888.4 CMOS Capacitive Sensors for Lab-on-Chip Applications	TK7888.4 Dynamic Reconfigurable Architectures and Transparent Optimization Techniques	TK7888.4 Robust Computing with Nano-scale Devices	Siguiente

Preliminaries -- System-Level Verification -- Block-Level Verification -- Top-Level Verification -- Summary and Conclusions.

Faced with the steadily increasing complexity and rapidly shortening time-to-market requirements designing electronic systems is a very challenging task. To manage this situation effectively the level of abstraction in modeling has been raised during the past years in the computer aided design community. Meanwhile, for the so-called system-level design the system description language SystemC has become the de facto standard. However, while modeling from abstract to synthesizable descriptions in combination with specification concepts like Transaction Level Modeling (TLM) leads to very good results, the verification quality is poor. The two main reasons are that (1) the existing SystemC verification techniques do not escort the different abstraction levels effectively and (2) in particular the resulting quality in terms of the covered functionality is only checked manually. Hence, due to the increasing design complexity the number of undetected errors is growing rapidly. Therefore a quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.