Silicon Nanowire Transistors [recurso electrónico] / by Ahmet Bindal, Sotoudeh Hamedi-Hagh.
Tipo de material: TextoEditor: Cham : Springer International Publishing : Imprint: Springer, 2016Edición: 1st ed. 2016Descripción: XIV, 165 p. 145 illus., 140 illus. in color. online resourceTipo de contenido: text Tipo de medio: computer Tipo de portador: online resourceISBN: 9783319271774Tema(s): Engineering | Electronic circuits | Nanotechnology | Engineering | Circuits and Systems | Electronic Circuits and Devices | NanotechnologyFormatos físicos adicionales: Printed edition:: Sin títuloClasificación CDD: 621.3815 Clasificación LoC:TK7888.4Recursos en línea: Libro electrónicoTipo de ítem | Biblioteca actual | Colección | Signatura | Copia número | Estado | Fecha de vencimiento | Código de barras |
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Libro Electrónico | Biblioteca Electrónica | Colección de Libros Electrónicos | 1 | No para préstamo |
Dual Work Function Silicon Nanowire MOS Transistors -- Single Work Function Silicon Nanowire MOS Transistors -- Spice Modeling For Analog and Digital Applications -- High-Speed Analog Applications -- Radio Frequency (RF) Applications -- SRAM Mega Cell Design for Digital Applications -- Field-Programmable-Gate-Array (FPGA) -- Integrate-And-Fire Spiking (IFS) Neuron -- Direct Sequence Spread Spectrum (DSSS) Base-Band Transmitter.-.
This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology?s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types of memory on the same chip, such as capacitive cells and transistors with floating gates that can be used as DRAMs and Flash memories.