TY  - BOOK
AU  - Sasao,Tsutomu
ED  - SpringerLink (Online service)
TI  - Memory-Based Logic Synthesis
SN  - 9781441981042
AV  - QC71.82-73.8 
U1  - 621.042 23
PY  - 2011///
CY  - New York, NY
PB  - Springer New York, Imprint: Springer
KW  - Computer aided design
KW  - Systems engineering
KW  - Energy
KW  - Energy, general
KW  - Circuits and Systems
KW  - Computer-Aided Engineering (CAD, CAE) and Design
N1  - Introduction -- Basic Elements -- Definitions and Basic Properties -- MUX-Based Synthesis -- Cascade-Based Synthesis -- Encoding Method -- Functions with Small C-Measures -- C-Measure of Sparse Functions -- Index Generation Functions -- Hash-Based Synthesis -- Reduction of the Number of Variables -- Various Realizations -- Conclusions
N2  - This book describes the synthesis of logic functions using memories. It is useful to design field programmable gate arrays (FPGAs) that contain both small-scale memories, called look-up tables (LUTs), and medium-scale memories, called embedded memories.  This is a valuable reference for both FPGA system designers and CAD tool developers, concerned with logic synthesis for FPGAs.  Anyone using logic gates to design logic circuits, you can benefit from the methods described in this book.  Describes in detail the synthesis of logic functions using memories;  Introduces a look-up tables (LUT) cascade as a new architecture for logic synthesis;  Shows logic design methods for index generation functions;  Introduces C-measure, which specifies the complexity of Boolean functions;  Introduces hash-based design methods, which efficiently synthesize index generation functions by pairs of smaller memories and can be applied to IP address tables, packet filtering, terminal access controllers, memory patch circuits, virus scanning circuits, intrusion detection circuits, fault map of memories, code converters and pattern matching.  
UR  - http://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-1-4419-8104-2
ER  -