TY  - BOOK
AU  - Hong,Dongwoo
AU  - Cheng,Kwang-Ting
ED  - SpringerLink (Online service)
TI  - Efficient Test Methodologies for High-Speed Serial Links
T2  - Lecture Notes in Electrical Engineering,
SN  - 9789048134434
AV  - TK7888.4 
U1  - 621.3815 23
PY  - 2010///
CY  - Dordrecht
PB  - Springer Netherlands
KW  - Engineering
KW  - Computer science
KW  - Systems engineering
KW  - Circuits and Systems
KW  - Register-Transfer-Level Implementation
N1  - An Efficient Jitter Measurement Technique -- BER Estimation for Linear Clock and Data Recovery Circuit -- BER Estimation for Non-linear Clock and Data Recovery Circuit -- Gaps in Timing Margining Test -- An Accurate Jitter Estimation Technique -- A Two-Tone Test Method for Continuous-Time Adaptive Equalizers -- Conclusions
N2  - With the increasing demand for higher data bandwidth, communication systems’ data rates have reached the multi-gigahertz range and even beyond. Advances in semiconductor technologies have accelerated the adoption of high-speed serial interfaces, such as PCI-Express, Serial-ATA, and XAUI, in order to mitigate the high pin-count and the data-channel skewing problems. However, with the increasing number of I/O pins and greater data rates, significant challenges arise for testing high-speed interfaces in terms of test cost and quality, especially in high volume manufacturing (HVM) environments. Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques
UR  - http://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-90-481-3443-4
ER  -