TY  - BOOK
AU  - Goossens,Sven
AU  - Chandrasekar,Karthik
AU  - Akesson,Benny
AU  - Goossens,Kees
ED  - SpringerLink (Online service)
TI  - Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-offs 
T2  - Embedded Systems,
SN  - 9783319320946
AV  - TK7888.4 
U1  - 621.3815 23
PY  - 2016///
CY  - Cham
PB  - Springer International Publishing, Imprint: Springer
KW  - Engineering
KW  - Microprocessors
KW  - Electronics
KW  - Microelectronics
KW  - Electronic circuits
KW  - Circuits and Systems
KW  - Processor Architectures
KW  - Electronics and Microelectronics, Instrumentation
N1  - Introduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols
N2  - This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template
UR  - http://148.231.10.114:2048/login?url=http://dx.doi.org/10.1007/978-3-319-32094-6
ER  -