TY  - BOOK
AU  - Haj-Yahya,Jawad
AU  - Mendelson,Avi
AU  - Ben Asher,Yosi
AU  - Chattopadhyay,Anupam
ED  - SpringerLink (Online service)
TI  - Energy Efficient High Performance Processors: Recent Approaches for Designing Green High Performance Computing 
T2  - Computer Architecture and Design Methodologies,
SN  - 9789811085543
AV  - TK7888.4 
U1  - 621.3815 23
PY  - 2018///
CY  - Singapore
PB  - Springer Singapore, Imprint: Springer
KW  - Electronic circuits
KW  - Microprocessors
KW  - Circuits and Systems
KW  - Processor Architectures
KW  - Electronic Circuits and Devices
N1  - Acceso multiusuario; Introduction -- Background -- DOEE: Dynamic Optimization framework for better Energy Efficiency -- Fine-grain Power Breakdown of Modern Out-Of-Order Cores and its implications on Skylake based systems -- Compiler-Directed Power Management for Superscalars -- SEEM: Symbolic Execution for Energy Modeling -- Related Works -- Conclusions and Future Work
N2  - This book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM). Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems
UR  - http://148.231.10.114:2048/login?url=https://doi.org/10.1007/978-981-10-8554-3
ER  -