TY - BOOK AU - Barkalov,Alexander AU - Titarenko,Larysa AU - Bieganowski,Jacek ED - SpringerLink (Online service) TI - Logic Synthesis for Finite State Machines Based on Linear Chains of States: Foundations, Recent Developments and Challenges T2 - Studies in Systems, Decision and Control, SN - 9783319598376 AV - Q342 U1 - 006.3 23 PY - 2018/// CY - Cham PB - Springer International Publishing, Imprint: Springer KW - Computational intelligence KW - Electronic circuits KW - Computational Intelligence KW - Circuits and Systems N1 - Acceso multiusuario; Introduction -- Finite state machines and field-programmable gate arrays -- Linear chains in FSMs -- Hardware reduction for Moore UFSMs -- Hardware reduction for Mealy UFSMs -- Hardware reduction for Moore NFSMs -- Hardware reduction for Moore XFSMs N2 - This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation. This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units UR - http://148.231.10.114:2048/login?url=https://doi.org/10.1007/978-3-319-59837-6 ER -