Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs [recurso electrónico] / by Jesús Ruiz-Amaya, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez.

Por: Ruiz-Amaya, Jesús [author.]Colaborador(es): Delgado-Restituto, Manuel [author.] | Rodríguez-Vázquez, Ángel [author.] | SpringerLink (Online service)Tipo de material: TextoTextoEditor: New York, NY : Springer New York : Imprint: Springer, 2011Descripción: XIII, 209p. 146 illus. online resourceTipo de contenido: text Tipo de medio: computer Tipo de portador: online resourceISBN: 9781441988461Tema(s): Engineering | Computer science | Systems engineering | Engineering | Circuits and Systems | Signal, Image and Speech Processing | Processor ArchitecturesFormatos físicos adicionales: Printed edition:: Sin títuloClasificación CDD: 621.3815 Clasificación LoC:TK7888.4Recursos en línea: Libro electrónicoTexto
Contenidos:
Pipeline ADC Overview -- Design Methodologies for Pipeline ADCs -- Pipeline ADC Electrical-level Synthesis Tool -- Behavioural Modeling of Pipeline ADCs -- Case Study: Design of a 10BIT@60MS Pipeline ADC -- Experimental Results and State of the Art -- Conclusions and Future Lines of Research.
En: Springer eBooksResumen: This book presents models and procedures to design pipeline analog-to-digital converters, compensating for device inaccuracies, so that high-performance specs can be met within short design cycles. These models are capable of capturing and predicting the behavior of pipeline data converters within less than half-a-bit deviation, versus transistor-level simulations.  As a result, far fewer model iterations are required across the design cycle. Models described in this book accurately predict transient behaviors, which are key to the performance of discrete-time systems and hence to the performance of pipeline data converters.  Describes efficient procedures for heirarchical top-down design of pipeline converters;  Presents new methodologies to reduce bottom-up iterations, through inherent embedding of transistor-level parameters, such as parasitic capacitances, transconductances, and saturation currents;   Provides mathematical details of behavioral models, includes descriptions of the synthesis methods and associated tools and illustrates models through case studies supported by silicon prototypes.        
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Libro Electrónico Biblioteca Electrónica
Colección de Libros Electrónicos TK7888.4 (Browse shelf(Abre debajo)) 1 No para préstamo 372194-2001

Pipeline ADC Overview -- Design Methodologies for Pipeline ADCs -- Pipeline ADC Electrical-level Synthesis Tool -- Behavioural Modeling of Pipeline ADCs -- Case Study: Design of a 10BIT@60MS Pipeline ADC -- Experimental Results and State of the Art -- Conclusions and Future Lines of Research.

This book presents models and procedures to design pipeline analog-to-digital converters, compensating for device inaccuracies, so that high-performance specs can be met within short design cycles. These models are capable of capturing and predicting the behavior of pipeline data converters within less than half-a-bit deviation, versus transistor-level simulations.  As a result, far fewer model iterations are required across the design cycle. Models described in this book accurately predict transient behaviors, which are key to the performance of discrete-time systems and hence to the performance of pipeline data converters.  Describes efficient procedures for heirarchical top-down design of pipeline converters;  Presents new methodologies to reduce bottom-up iterations, through inherent embedding of transistor-level parameters, such as parasitic capacitances, transconductances, and saturation currents;   Provides mathematical details of behavioral models, includes descriptions of the synthesis methods and associated tools and illustrates models through case studies supported by silicon prototypes.        

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