000			03364nam a22004455i 4500
001			u371764
003			SIRSI
005			20160812080146.0
007			cr nn 008mamaa
008			101029s2011 xxu| s |||| 0|eng d
020			_a9781441968654 _9978-1-4419-6865-4
040			_cMX-MeUAM
050		4	_aTK7888.4
082	0	4	_a621.3815 _223
100	1		_aHansson, Andreas. _eauthor.
245	1	0	_aOn-Chip Interconnect with aelite _h[recurso electrónico] : _bComposable and Predictable Systems / _cby Andreas Hansson, Kees Goossens.
264		1	_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2011.
300			_aX, 210 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aEmbedded Systems, _x2193-0155
520			_aOn-Chip Interconnect with aelite: Composable and Predictable Systems by: (Authors) Andreas Hansson Kees Goossens Embedded systems are comprised of components integrated on a single circuit, a System on Chip (SoC). One of the critical elements of such an SoC, and the focus of this work, is the on-chip interconnect that enables different components to communicate with each other. The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs. •Uses real-world illustrations extensively, in the form of case studies and examples that communicate the power of the methods presented; •Uses one consistent, running example throughout the book. This example is introduced in the introductory chapter and supports the presentation throughout the work, with additional details given in each chapter; •Content has both breadth (architecture, resource allocation, hardware/software instantiation, formal verification) and depth (block-level architecture description, allocation algorithms, complete run-time APIs, detailed formal models, complete case studies mapped to FPGAs); •Includes numerous case studies, e.g. a JPEG decoder, set-top box and digital radio design.
650		0	_aEngineering.
650		0	_aComputer aided design.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
700	1		_aGoossens, Kees. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781441964960
830		0	_aEmbedded Systems, _x2193-0155
856	4	0	_zLibro electrónico _uhttp://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-1-4419-6865-4
596			_a19
942			_cLIBRO_ELEC
999			_c199644 _d199644