000			03061nam a22004335i 4500
001			u372062
003			SIRSI
005			20160812080202.0
007			cr nn 008mamaa
008			101109s2011 xxu| s |||| 0|eng d
020			_a9781441979285 _9978-1-4419-7928-5
040			_cMX-MeUAM
050		4	_aTK7888.4
082	0	4	_a621.3815 _223
100	1		_aParvez, Husain. _eauthor.
245	1	0	_aApplication-Specific Mesh-based Heterogeneous FPGA Architectures _h[recurso electrónico] / _cby Husain Parvez, Habib Mehrez.
264		1	_aNew York, NY : _bSpringer New York, _c2011.
300			_aXVII, 150 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction -- State of the Art -- FPGA Layout Generation -- ASIF: Application Specific Inflexible FPGA -- ASIF using Heterogeneous Logic Blocks -- ASIF Hardware Generation -- Conclusion and Future Lines of Research.
520			_aLow volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However, the flexibility of FPGAs makes them much larger, slower, and more power consuming than their counterpart ASICs. Consequently, FPGAs are unsuitable for applications requiring high volume production, high performance or low power consumption. This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures.  It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required.  Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures. Presents a new exploration environment for mesh-based, heterogeneous FPGA architectures; Describes state-of-the-art techniques for reducing area requirements in FPGA architectures; Enables reduction in power required and increase in performance.
650		0	_aEngineering.
650		0	_aElectronics.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
700	1		_aMehrez, Habib. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781441979278
856	4	0	_zLibro electrónico _uhttp://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-1-4419-7928-5
596			_a19
942			_cLIBRO_ELEC
999			_c199942 _d199942