| 000 | 02775nam a22004455i 4500 | ||
|---|---|---|---|
| 001 | u374833 | ||
| 003 | SIRSI | ||
| 005 | 20160812084254.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 101029s2011 gw | s |||| 0|eng d | ||
| 020 |
_a9783642147036 _9978-3-642-14703-6 |
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| 040 | _cMX-MeUAM | ||
| 050 | 4 | _aTK1-9971 | |
| 082 | 0 | 4 |
_a621.382 _223 |
| 100 | 1 |
_aTian, Xiaohua. _eauthor. |
|
| 245 | 1 | 0 |
_aEntropy Coders of the H.264/AVC Standard _h[recurso electrónico] : _bAlgorithms and VLSI Architectures / _cby Xiaohua Tian, Thinh M. Le, Yong Lian. |
| 264 | 1 |
_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg : _bImprint: Springer, _c2011. |
|
| 300 |
_aXXIV, 180 p. _bonline resource. |
||
| 336 |
_atext _btxt _2rdacontent |
||
| 337 |
_acomputer _bc _2rdamedia |
||
| 338 |
_aonline resource _bcr _2rdacarrier |
||
| 347 |
_atext file _bPDF _2rda |
||
| 490 | 1 |
_aSignals and Communication Technology, _x1860-4862 |
|
| 505 | 0 | _aIntroduction to Video Compression -- Review of Arithmetic Coding and CABAC -- Review of Existing Statistical Codec Designs -- Design of a CABAC Encoder -- Efficient Architecture of Context Modeling of CABAC Encoder -- Design of System Bus Interface & Inter-connection of SoCbased CABAC Encoder. | |
| 520 | _aThis book presents a collection of algorithms and VLSI architectures of entropy (or statistical) codecs of recent video compression standards, with focus on the H.264/AVC standard. For any visual data compression scheme, there exists a combination of one, two, or all of the following three stages: spatial, temporal, and statistical compression. General readers are first introduced with the various algorithms of the statistical coders. The VLSI implementations are also reviewed and discussed. Readers with limited hardware design background are also introduced with a design methodology starting from performance-complexity analysis to software/ hardware co-simulation. A typical design of the Context-based Adaptive Binary Arithmetic Coding (CABAC) encoder is also presented in details. To support System-on-Chip design environment, the CABAC design is wrapped with a SoC-based Wishbone system bus interface. | ||
| 650 | 0 | _aEngineering. | |
| 650 | 0 | _aTelecommunication. | |
| 650 | 1 | 4 | _aEngineering. |
| 650 | 2 | 4 | _aCommunications Engineering, Networks. |
| 700 | 1 |
_aLe, Thinh M. _eauthor. |
|
| 700 | 1 |
_aLian, Yong. _eauthor. |
|
| 710 | 2 | _aSpringerLink (Online service) | |
| 773 | 0 | _tSpringer eBooks | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783642147029 |
| 830 | 0 |
_aSignals and Communication Technology, _x1860-4862 |
|
| 856 | 4 | 0 |
_zLibro electrónico _uhttp://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-3-642-14703-6 |
| 596 | _a19 | ||
| 942 | _cLIBRO_ELEC | ||
| 999 |
_c202713 _d202713 |
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