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007			cr nn 008mamaa
008			110414s2010 ne | s |||| 0|eng d
020			_a9789048130313 _9978-90-481-3031-3
040			_cMX-MeUAM
050		4	_aTK7888.4
082	0	4	_a621.3815 _223
100	1		_aNicopoulos, Chrysostomos. _eauthor.
245	1	0	_aNetwork-on-Chip Architectures _h[recurso electrónico] : _bA Holistic Design Exploration / _cby Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das.
264		1	_aDordrecht : _bSpringer Netherlands, _c2010.
300			_aXXII, 223p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aLecture Notes in Electrical Engineering, _x1876-1100 ; _v45
505	0		_aMICRO-Architectural Exploration -- A Baseline NoC Architecture -- ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39] -- RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40] -- Exploring FaultoTolerant Network-on-Chip Architectures [37] -- On the Effects of Process Variation in Network-on-Chip Architectures [45] -- MACRO-Architectural Exploration -- The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15] -- Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43] -- A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44] -- Digest of Additional NoC MACRO-Architectural Research -- Conclusions and Future Work.
520			_aThe continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning global wiring delays in many-core chips, and have recently crystallized into a significant research domain. On-chip networks instill a new flavor to communication research due to their inherently resource-constrained nature. Despite the lightweight character demanded of the NoC components, modern designs require ultra-low communication latencies in order to cope with inflating data bandwidths. The work presented in Network-on-Chip Architectures addresses these issues through a comprehensive exploration of the design space. The design aspects of the NoC are viewed through a penta-faceted prism encompassing five major issues: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. These five aspects serve as the fundamental design drivers and critical evaluation metrics in the quest for efficient NoC implementations. The research exploration employs a two-pronged approach: (a) MICRO-architectural innovations within the major NoC components, and (b) MACRO-architectural choices aiming to seamlessly merge the interconnection backbone with the remaining system modules. These two research threads and the aforementioned five key metrics mount a holistic and in-depth attack on most issues surrounding the design of NoCs in multi-core architectures.
650		0	_aEngineering.
650		0	_aComputer science.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aProcessor Architectures.
700	1		_aNarayanan, Vijaykrishnan. _eauthor.
700	1		_aDas, Chita R. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9789048130306
830		0	_aLecture Notes in Electrical Engineering, _x1876-1100 ; _v45
856	4	0	_zLibro electrónico _uhttp://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-90-481-3031-3
596			_a19
942			_cLIBRO_ELEC
999			_c205388 _d205388