000			03696nam a22004695i 4500
001			u377742
003			SIRSI
005			20160812084518.0
007			cr nn 008mamaa
008			100316s2010 ne | s |||| 0|eng d
020			_a9789048139170 _9978-90-481-3917-0
040			_cMX-MeUAM
050		4	_aTK1-9971
082	0	4	_a621.382 _223
100	1		_aJones, Keith. _eauthor.
245	1	4	_aThe Regularized Fast Hartley Transform _h[recurso electrónico] : _bOptimal Formulation of Real-Data Fast Fourier Transform for Silicon-Based Implementation in Resource-Constrained Environments / _cby Keith Jones.
264		1	_aDordrecht : _bSpringer Netherlands : _bImprint: Springer, _c2010.
300			_aXVII, 200p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aSignals and Communication Technology, _x1860-4862
505	0		_aBackground to Research -- Fast Solutions to Real-Data Discrete Fourier Transform -- The Discrete Hartley Transform -- Derivation of the Regularized Fast Hartley Transform -- Algorithm Design for Hardware-Based Computing Technologies -- Derivation of Area-Efficient and Scalable Parallel Architecture -- Design of Arithmetic Unit for Resource-Constrained Solution -- Computation of 2n-Point Real-Data Discrete Fourier Transform -- Applications of Regularized Fast Hartley Transform -- Summary and Conclusions.
520			_aWhen designing high-performance DSP systems for implementation with silicon-based computing technology, the oft-encountered problem of the real-data DFT is typically addressed by exploiting an existing complex-data FFT, which can easily result in an overly complex and resource-hungry solution. The research described in The Regularized Fast Hartley Transform: Optimal Formulation of Real-Data Fast Fourier Transform for Silicon-Based Implementation in Resource-Constrained Environments deals with the problem by exploiting directly the real-valued nature of the data and is targeted at those real-world applications, such as mobile communications, where size and power constraints play key roles in the design and implementation of an optimal solution. The Regularized Fast Hartley Transform provides the reader with the tools necessary to both understand the proposed new formulation and to implement simple design variations that offer clear implementational advantages, both practical and theoretical, over more conventional complex-data solutions to the problem. The highly-parallel formulation described is shown to lead to scalable and device-independent solutions to the latency-constrained version of the problem which are able to optimize the use of the available silicon resources, and thus to maximize the achievable computational density, thereby making the solution a genuine advance in the design and implementation of high-performance parallel FFT algorithms.
650		0	_aEngineering.
650		0	_aComputer Communication Networks.
650		0	_aMathematics.
650		0	_aTelecommunication.
650	1	4	_aEngineering.
650	2	4	_aCommunications Engineering, Networks.
650	2	4	_aComputer Communication Networks.
650	2	4	_aApplications of Mathematics.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9789048139163
830		0	_aSignals and Communication Technology, _x1860-4862
856	4	0	_zLibro electrónico _uhttp://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-90-481-3917-0
596			_a19
942			_cLIBRO_ELEC
999			_c205622 _d205622