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001			u378087
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005			20160812084536.0
007			cr nn 008mamaa
008			101029s2011 ne | s |||| 0|eng d
020			_a9789048197255 _9978-90-481-9725-5
040			_cMX-MeUAM
050		4	_aTK7800-8360
050		4	_aTK7874-7874.9
082	0	4	_a621.381 _223
100	1		_aZjajo, Amir. _eauthor.
245	1	0	_aLow-Power High-Resolution Analog to Digital Converters _h[recurso electrónico] : _bDesign, Test and Calibration / _cby Amir Zjajo, José Pineda de Gyvez.
264		1	_aDordrecht : _bSpringer Netherlands, _c2011.
300			_aXX, 250p. 100 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aAnalog Circuits and Signal Processing
505	0		_aForeword -- Abbrevations.- Symbols -- 1. Introduction -- 2. Analog to Digital Conversion -- 3. Design of Multi-Step A/D Converters -- 4. Multi-Step A/D Converter Testing -- 5. Multi-Step A/D Converter Debugging -- 6. Conclusions and Recommendations -- Appendix -- References -- Index.-.
520			_aWith the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
650		0	_aEngineering.
650		0	_aComputer aided design.
650		0	_aElectronics.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
700	1		_aPineda de Gyvez, José. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9789048197248
830		0	_aAnalog Circuits and Signal Processing
856	4	0	_zLibro electrónico _uhttp://148.231.10.114:2048/login?url=http://link.springer.com/book/10.1007/978-90-481-9725-5
596			_a19
942			_cLIBRO_ELEC
999			_c205967 _d205967