000 00926cam a2200253 i 4500
999 _c217321
_d217321
001 17727644
003 MX-MeUAM
005 20220707132625.0
008 170110s2013 maua frb 000 0 eng d
020 _a9780262019668 (hardcover)
040 _aDLC
_bspa
_cDLC
_erda
_dMX-MeUAM
041 1 _aeng
050 4 _aTK7885.7
_bP438 2013
100 1 _aPedroni, Volnei A.
245 1 0 _aFinite state machines in hardware :
_btheory and design (with VHDL and SystemVerilog) /
_cVolnei A. Pedroni.
260 _aCambridge, Massachusetts :
_bThe MIT Press,
_c2013.
300 _ax, 337 p. :
_bil. ;
_c24 cm
504 _aIncluye referencias bibliográficas e índice.
650 0 _aSystemVerilog (Computer hardware description language)
650 0 _aVHDL (Computer hardware description language)
650 0 _aSequential machine theory
_xData processing.
650 0 _aComputer systems
_xMathematical models.
942 _cLIBRO