000 | 03414nam a22005175i 4500 | ||
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001 | 978-3-319-24004-6 | ||
003 | DE-He213 | ||
005 | 20180206182943.0 | ||
007 | cr nn 008mamaa | ||
008 | 160118s2016 gw | s |||| 0|eng d | ||
020 |
_a9783319240046 _9978-3-319-24004-6 |
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050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
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072 | 7 |
_aTEC008010 _2bisacsh |
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082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aZhang, Chenxin. _eauthor. |
|
245 | 1 | 0 |
_aHeterogeneous Reconfigurable Processors for Real-Time Baseband Processing _h[recurso electrónico] : _bFrom Algorithm to Architecture / _cby Chenxin Zhang, Liang Liu, Viktor Öwall. |
250 | _a1st ed. 2016. | ||
264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2016. |
|
300 |
_aXIV, 195 p. 81 illus., 29 illus. in color. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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505 | 0 | _aIntroduction -- Digital Hardware Platforms -- Digital Baseband Processing -- The Reconfigurable Cell Array -- Multi-standard Digital Front-End Processing -- Multi-task MIMO Signal Processing -- Future Multi-user MIMO systems ? A Discussion -- Conclusion.-. | |
520 | _aThis book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G. ?Discusses reconfigurable architectures, including hardware building blocks such as processing elements, memory sub-systems, Network-on-Chip (NoC), and dynamic hardware reconfiguration; ?Describes a unique design and optimization methodology, applied to different areas and levels, including communication theory, hardware implementation, and software support; ?Demonstrates design trade-offs during different development phases and enables readers to apply similar techniques to various applications. | ||
650 | 0 | _aEngineering. | |
650 | 0 | _aMicroprocessors. | |
650 | 0 | _aElectronics. | |
650 | 0 | _aMicroelectronics. | |
650 | 0 | _aElectronic circuits. | |
650 | 1 | 4 | _aEngineering. |
650 | 2 | 4 | _aCircuits and Systems. |
650 | 2 | 4 | _aProcessor Architectures. |
650 | 2 | 4 | _aElectronics and Microelectronics, Instrumentation. |
700 | 1 |
_aLiu, Liang. _eauthor. |
|
700 | 1 |
_aÖwall, Viktor. _eauthor. |
|
710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9783319240022 |
856 | 4 | 0 |
_zLibro electrónico _uhttp://148.231.10.114:2048/login?url=http://dx.doi.org/10.1007/978-3-319-24004-6 |
912 | _aZDB-2-ENG | ||
942 | _cLIBRO_ELEC | ||
999 |
_c225659 _d225659 |