| 000 | 03897nam a22005655i 4500 | ||
|---|---|---|---|
| 001 | 978-3-319-66619-8 | ||
| 003 | DE-He213 | ||
| 005 | 20210201191503.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 171005s2018 gw | s |||| 0|eng d | ||
| 020 |
_a9783319666198 _9978-3-319-66619-8 |
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| 050 | 4 | _aTK7888.4 | |
| 072 | 7 |
_aTJFC _2bicssc |
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| 072 | 7 |
_aTEC008010 _2bisacsh |
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| 072 | 7 |
_aTJFC _2thema |
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| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aKhondkar, Progyna. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut |
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| 245 | 1 | 0 |
_aLow-Power Design and Power-Aware Verification _h[electronic resource] / _cby Progyna Khondkar. |
| 250 | _a1st ed. 2018. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2018. |
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| 300 |
_aXV, 155 p. 19 illus., 12 illus. in color. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 500 | _aAcceso multiusuario | ||
| 505 | 0 | _a1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References. . | |
| 520 | _aUntil now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers. . | ||
| 541 |
_fUABC ; _cTemporal ; _d01/01/2021-12/31/2023. |
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| 650 | 0 | _aElectronic circuits. | |
| 650 | 0 | _aSoftware engineering. | |
| 650 | 0 | _aMicroprocessors. | |
| 650 | 0 | _aComputer software-Reusability. | |
| 650 | 1 | 4 |
_aCircuits and Systems. _0https://scigraph.springernature.com/ontologies/product-market-codes/T24068 |
| 650 | 2 | 4 |
_aSoftware Engineering. _0https://scigraph.springernature.com/ontologies/product-market-codes/I14029 |
| 650 | 2 | 4 |
_aProcessor Architectures. _0https://scigraph.springernature.com/ontologies/product-market-codes/I13014 |
| 650 | 2 | 4 |
_aPerformance and Reliability. _0https://scigraph.springernature.com/ontologies/product-market-codes/I12077 |
| 710 | 2 | _aSpringerLink (Online service) | |
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319666181 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319666204 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319882864 |
| 856 | 4 | 0 |
_zLibro electrónico _uhttp://148.231.10.114:2048/login?url=https://doi.org/10.1007/978-3-319-66619-8 |
| 912 | _aZDB-2-ENG | ||
| 912 | _aZDB-2-SXE | ||
| 942 | _cLIBRO_ELEC | ||
| 999 |
_c244018 _d244017 |
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