000 | 04468nam a22006015i 4500 | ||
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001 | 978-3-319-74382-0 | ||
003 | DE-He213 | ||
005 | 20210201191506.0 | ||
007 | cr nn 008mamaa | ||
008 | 180314s2018 gw | s |||| 0|eng d | ||
020 |
_a9783319743820 _9978-3-319-74382-0 |
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050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
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072 | 7 |
_aTEC008010 _2bisacsh |
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072 | 7 |
_aTJFC _2thema |
|
082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aBuccella, Pietro. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut |
|
245 | 1 | 0 |
_aParasitic Substrate Coupling in High Voltage Integrated Circuits _h[electronic resource] : _bMinority and Majority Carriers Propagation in Semiconductor Substrate / _cby Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese. |
250 | _a1st ed. 2018. | ||
264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2018. |
|
300 |
_aXVII, 183 p. 124 illus., 73 illus. in color. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
||
490 | 1 |
_aAnalog Circuits and Signal Processing, _x1872-082X |
|
500 | _aAcceso multiusuario | ||
505 | 0 | _aChapter1: Overview of Parasitic Substrate Coupling -- Chapter2: Design Challenges in High Voltage ICs -- Chapter3: Substrate Modeling with Parasitic Transistors -- Chapter4: TCAD Validation of the Model -- Chapter5: Extraction Tool for the Substrate Network -- Chapter6: Parasitic Bipolar Transistors in Benchmark Structures -- Chapter7: Substrate Coupling Analysis and Evaluation of Protection Strategies. | |
520 | _aThis book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools. The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits. The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis. Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits; Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate; Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices; Offers design guidelines to reduce couplings by adding specific test protections. | ||
541 |
_fUABC ; _cTemporal ; _d01/01/2021-12/31/2023. |
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650 | 0 | _aElectronic circuits. | |
650 | 0 | _aElectronics. | |
650 | 0 | _aMicroelectronics. | |
650 | 1 | 4 |
_aCircuits and Systems. _0https://scigraph.springernature.com/ontologies/product-market-codes/T24068 |
650 | 2 | 4 |
_aElectronic Circuits and Devices. _0https://scigraph.springernature.com/ontologies/product-market-codes/P31010 |
650 | 2 | 4 |
_aElectronics and Microelectronics, Instrumentation. _0https://scigraph.springernature.com/ontologies/product-market-codes/T24027 |
700 | 1 |
_aStefanucci, Camillo. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut |
|
700 | 1 |
_aKayal, Maher. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut |
|
700 | 1 |
_aSallese, Jean-Michel. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut |
|
710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer Nature eBook | |
776 | 0 | 8 |
_iPrinted edition: _z9783319743813 |
776 | 0 | 8 |
_iPrinted edition: _z9783319743837 |
776 | 0 | 8 |
_iPrinted edition: _z9783030089764 |
830 | 0 |
_aAnalog Circuits and Signal Processing, _x1872-082X |
|
856 | 4 | 0 |
_zLibro electrónico _uhttp://148.231.10.114:2048/login?url=https://doi.org/10.1007/978-3-319-74382-0 |
912 | _aZDB-2-ENG | ||
912 | _aZDB-2-SXE | ||
942 | _cLIBRO_ELEC | ||
999 |
_c244078 _d244077 |