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020 _a9783031382307
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082 0 4 _a621.3815
_223
100 1 _aJain, Vikram.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
245 1 0 _aTowards Heterogeneous Multi-core Systems-on-Chip for Edge Machine Learning
_h[electronic resource] :
_bJourney from Single-core Acceleration to Multi-core Heterogeneous Systems /
_cby Vikram Jain, Marian Verhelst.
250 _a1st ed. 2024.
264 1 _aCham :
_bSpringer Nature Switzerland :
_bImprint: Springer,
_c2024.
300 _aXXIII, 186 p. 93 illus., 83 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aChapter 1: Introduction -- Chapter 2 Algorithmic Background for Machine Learning -- Chapter 3 Scoping the Landscape of (Extreme) Edge Machine Learning Processors -- Chapter 4 Hardware-Software Co-optimization through Design Space Exploration -- Chapter 5 Energy Efficient Single-core Hardware Acceleration -- Chapter 6 TinyVers: A Tiny Versatile All-Digital Heterogeneous Multi-core System-on-Chip -- Chapter 7 DIANA: Digital and ANAlog Heterogeneous Multi-core System-on-Chip -- Chapter 8 Networks-on-chip to Enable Large-scale Multi-core ML Acceleration -- Chapter 9 Conclusion.
520 _aThis book explores and motivates the need for building homogeneous and heterogeneous multi-core systems for machine learning to enable flexibility and energy-efficiency. Coverage focuses on a key aspect of the challenges of (extreme-)edge-computing, i.e., design of energy-efficient and flexible hardware architectures, and hardware-software co-optimization strategies to enable early design space exploration of hardware architectures. The authors investigate possible design solutions for building single-core specialized hardware accelerators for machine learning and motivates the need for building homogeneous and heterogeneous multi-core systems to enable flexibility and energy-efficiency. The advantages of scaling to heterogeneous multi-core systems are shown through the implementation of multiple test chips and architectural optimizations. Discusses the need for scaling to multi-core systems for machine learning and several architectural and software optimizations; Covers single-core, homogeneous and heterogeneous multi-core Systems-on-chip for machine learning applications; Discusses the benefits of heterogeneity in the context of machine learning. .
541 _fUABC ;
_cPerpetuidad
650 0 _aElectronic circuits.
650 0 _aEmbedded computer systems.
650 0 _aMachine learning.
650 0 _aMicroprocessors.
650 0 _aComputer architecture.
650 1 4 _aElectronic Circuits and Systems.
650 2 4 _aEmbedded Systems.
650 2 4 _aMachine Learning.
650 2 4 _aProcessor Architectures.
700 1 _aVerhelst, Marian.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
710 2 _aSpringerLink (Online service)
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783031382291
776 0 8 _iPrinted edition:
_z9783031382314
776 0 8 _iPrinted edition:
_z9783031382321
856 4 0 _zLibro electrónico
_uhttp://libcon.rec.uabc.mx:2048/login?url=https://doi.org/10.1007/978-3-031-38230-7
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cLIBRO_ELEC
999 _c273426
_d273425