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001 978-3-031-37989-5
003 DE-He213
005 20250516155922.0
007 cr nn 008mamaa
008 230922s2024 sz | s |||| 0|eng d
020 _a9783031379895
_9978-3-031-37989-5
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aZamiri Azar, Kimia.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
245 1 0 _aUnderstanding Logic Locking
_h[electronic resource] /
_cby Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor.
250 _a1st ed. 2024.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2024.
300 _aXVI, 381 p. 1 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aBasics of VLSI Design -- Basics of VLSI Testing and Debug -- IP Protection in VLSI Design: A Historical View -- Making a Case for Logic Locking -- Fundamentals of Logic Locking -- Infrastructure around Logic Locking -- Impact of Satisfiability Solvers on Logic Locking -- Post-Satisfiability Era: Countermeasures and Threats -- Design-for-Testability and its Impact on Logic Locking -- Emergence of Cutting-edge Technologies on Logic Locking -- Logic Locking in Future IC Supply Chain Environments -- Multilayer Approach to Logic Locking -- A Step-by-Step Guide for Protecting/Locking Your IP -- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP.
520 _aThis book demonstrates the breadth and depth of IP protection through logic locking, considering both attacker/adversary and defender/designer perspectives. The authors draw a semi-chronological picture of the evolution of logic locking during the last decade, gathering and describing all the DO's and DON'Ts in this approach. They describe simple-to-follow scenarios and guide readers to navigate/identify threat models and design/evaluation flow for further studies. Readers will gain a comprehensive understanding of all fundamentals of logic locking. Covers modern VLSI design, testability and debug, and hardware security threats at different levels of abstraction; Provides a comprehensive overview of logic locking techniques and their applications to hardware security; Covers logic locking from implementation to evaluation, different assumptions, models and abstraction layers.
541 _fUABC ;
_cPerpetuidad
650 0 _aElectronic circuit design.
650 0 _aEmbedded computer systems.
650 0 _aElectronic circuits.
650 1 4 _aElectronics Design and Verification.
650 2 4 _aEmbedded Systems.
650 2 4 _aElectronic Circuits and Systems.
700 1 _aMardani Kamali, Hadi.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
700 1 _aFarahmandi, Farimah.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
700 1 _aTehranipoor, Mark.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
710 2 _aSpringerLink (Online service)
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783031379888
776 0 8 _iPrinted edition:
_z9783031379901
776 0 8 _iPrinted edition:
_z9783031379918
856 4 0 _zLibro electrónico
_uhttp://libcon.rec.uabc.mx:2048/login?url=https://doi.org/10.1007/978-3-031-37989-5
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cLIBRO_ELEC
999 _c273439
_d273438