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001			978-981-97-3477-1
003			DE-He213
005			20250516160116.0
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008			240802s2024 si | s |||| 0|eng d
020			_a9789819734771 _9978-981-97-3477-1
050		4	_aTK7800-8360
072		7	_aTJF _2bicssc
072		7	_aTEC008000 _2bisacsh
072		7	_aTJF _2thema
082	0	4	_a621.381 _223
100	1		_aYue, Jinshan. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
245	1	0	_aHigh Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture _h[electronic resource] / _cby Jinshan Yue.
250			_a1st ed. 2024.
264		1	_aSingapore : _bSpringer Nature Singapore : _bImprint: Springer, _c2024.
300			_aXVI, 118 p. 81 illus., 78 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aSpringer Theses, Recognizing Outstanding Ph.D. Research, _x2190-5061
505	0		_aIntroduction -- Basis and research status of neural network processor -- Neural network processor for specific kernel optimized data reuse -- Neural network processor with frequency domain compression algorithm optimization -- Neural network processor combining digital and computing in memory architecture -- Digital computing in memory neural network processor supporting large scale models -- Conclusion and prospect.
520			_aNeural network (NN) algorithms are driving the rapid development of modern artificial intelligence (AI). The energy-efficient NN processor has become an urgent requirement for the practical NN applications on widespread low-power AI devices. To address this challenge, this dissertation investigates pure-digital and digital computing-in-memory (digital-CIM) solutions and carries out four major studies. For pure-digital NN processors, this book analyses the insufficient data reuse in conventional architectures and proposes a kernel-optimized NN processor. This dissertation adopts a structural frequency-domain compression algorithm, named CirCNN. The fabricated processor shows 8.1x/4.2x area/energy efficiency compared to the state-of-the-art NN processor. For digital-CIM NN processors, this dissertation combines the flexibility of digital circuits with the high energy efficiency of CIM. The fabricated CIM processor validates the sparsity improvement of the CIM architecture for the first time. This dissertation further designs a processor that considers the weight updating problem on the CIM architecture for the first time. This dissertation demonstrates that the combination of digital and CIM circuits is a promising technical route for an energy-efficient NN processor, which can promote the large-scale application of low-power AI devices. .
541			_fUABC ; _cPerpetuidad
650		0	_aElectronics.
650		0	_aElectronic circuits.
650		0	_aMicroprocessors.
650		0	_aComputer architecture.
650		0	_aComputational intelligence.
650	1	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aElectronic Circuits and Systems.
650	2	4	_aProcessor Architectures.
650	2	4	_aComputational Intelligence.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer Nature eBook
776	0	8	_iPrinted edition: _z9789819734764
776	0	8	_iPrinted edition: _z9789819734788
776	0	8	_iPrinted edition: _z9789819734795
830		0	_aSpringer Theses, Recognizing Outstanding Ph.D. Research, _x2190-5061
856	4	0	_zLibro electrónico _uhttp://libcon.rec.uabc.mx:2048/login?url=https://doi.org/10.1007/978-981-97-3477-1
912			_aZDB-2-ENG
912			_aZDB-2-SXE
942			_cLIBRO_ELEC
999			_c275924 _d275923