| 000 | 01020nam a22002417a 4500 | ||
|---|---|---|---|
| 003 | MX-MeUAM | ||
| 005 | 20250605104708.0 | ||
| 008 | 250605s2017 orud frb 001 0 eng d | ||
| 020 | _a9781546776345 | ||
| 020 | _a1546776346 | ||
| 040 |
_aMX-MeUAM _bspa _cMX-MeUAM |
||
| 050 | 4 |
_aTK7885.7 _bS88 2017 |
|
| 100 | 1 |
_aSutherland, Stuart, _d1953- _938553 |
|
| 245 | 1 | 0 |
_aRTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design / _cStuart Sutherland |
| 246 | 3 | 0 | _aRTL modeling with System Verilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design |
| 260 |
_aTualatin, OR : _bSutherland HDL, _c2017. |
||
| 300 |
_axxxi, 453 p. : _bgráficas ; _c23 cm. |
||
| 504 | _aIncluye referencias bibliográficas e índice. | ||
| 650 | 4 | _aVerilog (lenguaje de descripción de hardware de computadora). | |
| 650 | 7 |
_aComputadores electrónicos digitales _xDiseños y construcción. _2lemb |
|
| 650 | 7 |
_aSimulación por computadores. _2lemb |
|
| 942 | _cLIBRO | ||
| 999 |
_c278156 _d278155 |
||